A conventional approach to implement a write driver for an embedded non-volatile memory, which is currently known in the art, is by having a two-stack NMOS circuit array. These write drivers/BL drivers help to pull the bitline (BL) to ground during the write or program operation of a MTPM device. A number of wordlines (WLs) could share this two-stack NMOS BL driver.
Accordingly using current technology, there is a limitation to the amount of WLs that are possible to include in the MTPM array, since the number of WLs are limited by the BL drop that is tolerable during the programming operations. Additionally, the conventional use of BL drivers used in these memory devices limits the space available for other components, and decreases the memory cell area efficiency.
Referring to FIGS. 1 and 2, a schematic diagram of an IC structure of a conventional twin-cell MTPM 101, and a table with modes of operation settings are shown. Conventional MTPMs utilize twin-cell architecture, where a twin-cell is composed of two transistors, via a true transistor, complement transistor, a true bitline (BLT) and a complement bitline (BLC). These components share a common sourceline (SL), with a second pair of twin-cells as shown in FIG. 1. Though only two twin-cells are shown, in principle, there could be many twin-cells sharing common SL, BLT and BLC. In the conventional structure, the MTPM is composed primarily of these aforementioned transistors and the aforementioned three tracks, BLT, BLC, and SL, and WLs driving the twin-cells. In order to accomplish a programming function, the system must (1) apply a high voltage (e.g., 2 V) to the WL, (2) apply a relatively high voltage (e.g., 1.5 V) to the SL and (3) drive a BL to ground. The write current is typically high (e.g., 1.5 mA) which results in significant bitline (BL) voltage drop. In comparison, under normal read operations the current is usually less than a few hundred μA (e.g., 300 μA). Furthermore, during conventional programming operations in one cell, the other cells are turned off by having their Wits set at 0V.
Referring to FIG. 3, a conventional 4×1 MTPM array 200 with four sets of twin-cells is shown. The conventional 4×1 MTPM array 200 with four sets of twin-cells, contains a series of four transistors, a BLT, a BLC, a SL, a first WL, a second WL and a bitline driver and multiplexer (MUX) 210. These BL drivers are comparatively large in size, and contribute toward the BL drop in the MTPM array 200 during programming. One bit of data (1/0) is stored in twin-cell by pulling either BLT (1) or BLC (0) to ground through the corresponding BL driver, and having the appropriate WL turned on at a high voltage. The worst case BL drop is seen by the twin-cell farthest from the BL driver, which sees the entire wire drop/IR drop along the BL, followed by the VDS drop at the BL driver.